In many systems, a dedicated link carries both low-priority and high-priority traffic. Low-priority traffic can be lengthy and cause high-priority traffic to incur greater than acceptable latencies.
A software example of this is type of latency is interrupt processing for microprocessors. An interrupt causes software to begin execution of an alternate code stream, thereby delaying normal code processing.
A hardware example of this is the PCI Bus “Latency Timeout” protocol, where a central arbiter can force a bus master to get off the shared bus to allow another master to perform a transaction.
In both the software and hardware examples, the time to switch over to the interrupting transaction can be arbitrary and significant. Accordingly, improved and faster techniques for switching from low-priority to high-priority traffic on a dedicated link are required.